14 DAY TRIAL // Announced at the beginning of May, Intel's 3D Tri-Gate technology has offered the Santa Clara chip giant a huge advantage in transistor manufacturing, but GlobalFoundries isn't willing to let this slide and is currently working on developing its own 3D chip fabrication process.
This information was provided by Dirk Wristers, the company's VP of technology and integration engineering, in an interview with the bit-tech publication. While details were scarce, Wristers did state that the foundry is having ‘3D activity.’
In addition, Wristers also talked about GlobalFoundries production process roadmap and, in particular, the company's plans to stick with the gate-first production method for the 28nm node.
Gate-first will be used until 2013, when the foundry moves to the 20nm fabrication process.
The difference between the two technologies lies in the timing when the metal electrode is deposited, before or after the high-temperature activation anneal(s) of the flow, and gate-first, at least in theory, allows customers to transition to a lower manufacturing node without having to redesign their chips.
Furthermore, Wristers also stated that gate-first saves around 10-20 per cent die space at the 28nm node over the gate-last process, which is currently being used both by Intel and TSMC.
Despite the advantages that gate-first brings to GlobalFoundries at this time, the company still plans to transition to gate-last with its 20nm fabrication process. This move should enable the foundry to achieve a 50 per cent reduction in the size of SRAM and logic circuits, when compared with 28nm production.
According to Wristers, this is caused by the fact that, at 20nm, “density and scaling benefits of gate-first high-K metal gate no longer apply because of patterning-dominated lithography restrictions.”
Moving even further into the future, Wristers also confirmed that research and development of 14nm transistors is ‘well underway’ and that the foundry is looking into all sort of novel approaches for this production node. These include Multi-gate FinFETs as well as a series of source mask optimizations for improving pattern fidelity.