14 DAY TRIAL // MeP-h1, the new high-end processor core from Toshiba is the first configurable microprocessor to achieve a 1GHz clock speed an dis based on Toshiba's "Media embedded Processor" (MeP) architecture for digital consumer and other high performance SoCs.
Toshiba developed its first MeP core, MeP-c1 which had a 5-stage pipeline structure in 2001. Toshiba expanded MeP functionality, creating its line of c-series products, with the MeP-c2 and MeP-c3. The new core announced today, MeP-h1, introduces a 9-stage pipeline structure as the first core in the new high-performance h series. Toshiba is also developing MeP-c4, an enhanced c-series core.
The new core is also optimized for design of high-performance customized processors by integration of a reorder buffer circuit that manages and shortens waiting cycles for user extension instructions.
The present implementation of the core was manufactured with 65nanometer (nm) process technology, and that too contributed to achieving the 1GHz clock speed. The new configurable processor core is designed with register transfer level description and can be manufactured with other process technology, including 90nm technology.
The details of the processor and its technology were announced today ( August 16, local time ) at HOT CHIPS17, the international processor conference that opened at Stanford University on August 14.
MeP main features:
High-speed media processing ( image and audio ) Customizable configuration, including embedded-memory capacity Extensibility of hardware allowing easy addition of functions
These features contribute to shorter development times for SoC that integrate complicated functions, reducing the development time for digital products.