14 DAY TRIAL // A revolutionary new polymorphous microprocessor architecture will break all records in terms of processing speed, having the potential of reaching trillions of calculations per second.
For the past seven years the research team, led by Professors Doug Burger, Stephen Keckler and Kathryn McKinley, has been working on the design of the processor, an updated cross-platform compiler and the instruction set architecture needed to run it.
TRIPS, which stands for Tera-op Reliable Intelligently adaptive Processing System, is a chip architecture developed in collaboration with IBM's Austin Research Lab. The Defense Advanced Research Projects Agency is helping fund the effort with an $11.1 million grant.
It is a 170 million transistor custom ASIC designed in a 130nm technology that can perform far more tasks simultaneously than other chips, and the prototype will be shown off and detailed on April 30.
The prototype contains two processing cores. Each core can issue 16 operations per cycle. In all, the chip can handle 1,024 instructions at once. Most commercial chips only have a handful of instructions in flight at any given time.
TRIPS is a demonstration of a new class of processing architectures called Explicit Data Graph Execution (EDGE). Unlike conventional architectures that process one instruction at a time, EDGE can process large blocks of information all at once and more efficiently.
Its architecture is composed of many copies of a small number of replicated tiles, reducing complexity and improving ease of design.
Current "multicore" processing technologies increase speed by adding more processors, which individually may not be any faster than previous processors.
Adding processors shifts the burden of obtaining better performance to software programmers, who must assume the difficult task of rewriting their code to run well on a potentially large number of processors. "EDGE technology offers an alternative approach when the race to multicore runs out of Steam," said Keckler, associate professor of computer sciences.
The prototype is the first on a roadmap that will lead to ultra-powerful, flexible processors implemented in nanoscale applications. This technology is expected to have significant impact on the computing industry. Though the prototype contains two 16-wide processors per chip, the research team aims to scale this up with further development.