14 DAY TRIAL // Texas Instrument announced today that they have developed the first integrated PLL registered memory modules using dual in-line memory arrangement (RDIMM). They also pointed out that the memory will run at DDR3-800/1066 speeds at first.
The chip - named SN74SSTE32882 - is wrapped in a 176-pin BGA package and currently uses 130nm technology; however, chips are expected to be produced in smaller manufacturing technologies. For example, 78 nm DDR3 chips have already been presented by Micron with Samsung and Hynix trailing not too far behind. Using a new design of integrated PLL chips, TI hopes to eliminate the need of memory tuning in order to develop an easier way to manage memory chips especially when running in high performance and server architectures.
DDR3 will be the current standard in memory chips after DDR2 phases out. First introduced memories will work at a maximum of 800/1066MHz DDR, but will require lower voltage (1.5V). Translated into power usage, DDR3 will be more energy efficient than DDR2. 2007 will come with higher speeds for DDR3, first 1333MHz DDR speed will be introduced and later, maybe in the beginning of 2008, even an amazing 1600MHZ DDR, which will probably match future CPU FSB.
P35 and G33 INTEL chipsets from the "Bearlake" family will be the first to introduce DDR3 to the masses. Soon, the enthusiast oriented X38 will follow, adding extensive memory tuning capabilities to DDR3.
Micron already pointed out that they plan to mass produce DDR3 chips from the 2nd quarter of 2007. As for TI's SN74SSTE32882, it will sample today and should probably enter production by the autumn of 2007.