14 DAY TRIAL // AMD has great hopes for its new high-end generation of processors, all of them based on the Barcelona core and on the new well-established quad core architecture. During AMD's Analysts Day the company revealed much of its future roadmap for computer processors, chipsets and graphics chips. Among the details that 'slipped' were important information about the soon to come Barcelona based processors. The native quad core processors are a vital part in the company's strategy against Intel as they are aimed at competing with the Xeon processor line represented by the 65 nanometer Clovertown and the yet to be released 45nm Harpertown. Between the AMD quad core design and the Intel one there is a striking difference, as Intel processors are not "true" native quad core, but use a two dual core design linked through a data bus, while AMD rook the long road and designed an entire quad core architecture on a single silicon chip. Theoretically, both approaches have a number of advantages and disadvantages as well.
Intel's design of two dual core chips put together on a single silicon layer is known as a multi-chip module (MCM for short) design. Its main advantage is that it took little time to be implemented and fewer resources were used in the research and development process. The disadvantage hit in the performance department because the Xeon MCM design requires data transfer buses to be traversed in order to access data, even for data stored on another core and this approach is much slower than a direct core-to-core transfer. AMD's design team opted for a radical approach, going for a "true" native quad core processor, where the cores can communicate with each other without the need to go through the much slower data bus. The main advantage of this design will probably be seen in benchmarks and real life situations because, at least theoretically, the AMD processors are superior from the engineers' point of view. The bad part of the "true" quad cores from AMD is that it took a long time to design and implement, giving Intel almost a full year lead on the market. Another problem is that the yields are reduced and fabrication costs are higher.
Even if the Barcelona quad core processors are not really different from their older K8 brothers that ruled the market in 2003, there are still many improvements in the core architecture that go beyond the obvious quad core approach. According to the AMD information revealed to the press, there are four major areas that received special attention: power saving, performance improvement, native virtualization support and enhancements of the memory controller. As the Barcelona based processors will emerge in a world that becomes more concerned about its environment (about time, I would say), power saving features implemented at a hardware level are a must. The new technologies come as a continuation of the Cool'n'Quiet power saving implementation from the K8 generation of processors.
"Independent dynamic core technology" is aimed at reducing operating frequency across all four cores dynamically, so each core may have a different running frequency depending on its current workload. Present day power saving technology found in multi core processors will keep idle cores at a high frequency if there is even one core that runs a complicated series of tasks. "For example, if you're running one intensive application which only utilises a single core, this core will be clocked at full speed while the other three cores will idle in their lowest state of power consumption". The frequency scaling does not apply only to the processor's cores as the memory controller is able to scale its clock speed depending on the workload, rather than run at full core speed for extended periods of time when being idle.
"AMD CoolCore Technology" is the implementation of the idea that a processor should be able to power down parts of itself that are not needed in order to save power and decrease temperature by adding additional gates to transistors. "In other words, Barcelona has far more control with regard to shutting down parts of the CPU core to save power when they are not required - For example, floating-point units and the like can be switched off when they aren't in use". Unfortunately, this technology does not allow the shutting down of an entire core according to the site Hexus.
"Dual Dynamic Power Management" allows different CPU and memory controller voltages, so they can be adjusted according to the present workload and thus opening the way for additional power savings, unlike previous generations of processors where voltages were tied together. For the CPU cores, the voltage is dictated by the voltage needed by the core with the highest workload.
In order to address the ever increasing need for more performance and processing power expected from every new generation of CPUs, AMD introduced a number of technologies that should help the company win back the performance crown from Intel. "Wide floating-point accelerator" means that just like Intel's Core 2-based CPUs, the Barcelona processors will come with a "128-bit wide floating-point pipeline, doubled from the 64-bit pipeline found in the original K8 architecture" that should result in a big performance gain when "handling floating-point data and calculations".
"Balanced Smart Cache" refers to the fact that each core in the Barcelona design has its own level two of cache memory - 512KB for each core - and a shared level three of cache that is bigger - 2MB - to be shared by all CPU cores. The L3 cache acts as a storage unit for "data evicted from the cores' L2 caches, as well as for pre-fetched data that is likely to be needed by more than one core".
Closely linked to the performance issue of current processors is the virtualization support that enjoys a lot of advertising in the corporate IT environment nowadays. In a move that will hopefully win back some of the server market shares, AMD introduced the "Rapid Virtualisation Indexing" technology that "allows virtual machine memory-lookups to be carried out in hardware".
A last interesting piece of technology that is aimed at increasing performance on systems using the Barcelona quad core processors is the "Memory Optimiser Technology" that claims to drastically increase available memory bandwidth compared to the K8 processors running at the same speed. "Improved Core and DRAM pre-fetchers that predict what data will be needed by the processor based on patterns of access - and pull it into cache - help to mask the latency caused by having to access data from memory. Write-bursting is used to minimise the penalty for switching the memory-controller between read and write operations. This sees write requests stored in a buffer and then all carried out in sequence once the buffer is full. Unfortunately, it is unclear if this buffer can be read from when requests are made to read buffered data or whether, instead, data has to be written to memory and accessed from there", according to Hexus.
Even if AMD did not set a precise date for its Barcelona quad core processors to hit the market, it is known that they will appear sometime in August. According to AMD the clock speeds of the new processors will stay at first in the 2GHz range, but there are rumors that for the high end market, faster processors will gradually become available, as the manufacturing company demonstrated, not so long ago, the existence of a Phenom processor that reached the speed of 3GHz with standard air cooling.