14 DAY TRIAL // AMD has big plans for its near future Server CPU lines. Earlier this year, AMD announced the upcoming Torrenza technology, opening up its Opteron platform to the industry. This would allow other manufacturers to develop add-in components that are able to communicate directly with the CPU and memory. Even more so, AMD mentioned that Torrenza allows companies to create graphics-physics accelerators and co-processors that can be directly inserted in an Opteron socket.
This week, at IDF, Intel decided to counterattack and announced plans concerning its very own open chipset platform codenamed Geneseo. This comes quite unexpected, as Intel is renowned for thoroughly guarding its past and present platforms. First of all, Intel aims at developing an alternative to AMD's Hypertransport technology. This implies the development of a much faster pathway than PCI Express. Intel plans to interface devices directly to the FSB, allowing them to communicate much faster with the CPU and memory. Just as AMD, Intel will allow non-proprietary chips to plug in a Xeon socket and work parallel to the main CPU(s). It will be interesting to see how companies would react to such a move from Intel, when AMD's Torrenza announcements propelled it fairly well into the enterprise market.
Intel finally revealed its intentions to integrate memory controllers onto processors. AMD has been doing this for some years now, starting with its first Opteron CPUs. The open technologies are expected to be implemented in 2008 for Itanium and in 2009 for Xeon. Intel is currently working with several companies to develop compatible co-processors.
Intel also announced that it will be shipping around 1 million Quad Core units before AMD could ship a single one. In addition, Intel plans to include two new 45 nm fab locations and researches into the tera-flop technology.