14 DAY TRIAL // Intel Corporation has announced completing the development of the next-generation 32 nanometer manufacturing process, which would allow for the shrinking of the chips to a billionth of a meter. According to the company, the new fabrication technology will permit the chip maker to manufacture even more energy-efficient, denser and higher performing transistors. The Santa Clara based firm has stated that it is on track with entering production on the new process in the fourth quarter of the next year.
Intel revealed its plans to provide details on the 32nm process technology during a presentation at the International Electron Devices Meeting (IEDM) that will be held next week in San Francisco. The completion of the 32nm technology's development phase and the readiness for production announced prove that the chip maker is still focused on its plans called the “tick-tock” strategy referring to an already presented product and manufacturing cadence.
The company aims at introducing an entirely new processor micro-architecture which would be complemented by a fresh manufacturing process about every 12 months, something that no one else has done before. Should the company succeed in its effort to produce 32nm chips in 2009, it would be the fourth consecutive year it manages to complete its goal.
According to the Intel 32nm paper and presentation, the new logic technology incorporates second-generation high-k + metal gate technology, 193nm immersion lithography for critical patterning layers and enhanced transistor strain techniques. The performance and energy efficiency of Intel processors are greatly enhanced through these features. According to the paper, the manufacturing process comes with the highest transistor performance and the highest transistor density any 32nm technology announced in the industry would feature.
“Our manufacturing prowess and resulting products have helped us widen our lead in computing performance and battery life for Intel-based laptops, servers and desktops,” said Mark Bohr, Intel Senior Fellow and director of process architecture and integration. “As we’ve shown this year, the manufacturing strategy and execution have also given us the ability to create entirely new product lines for MIDs, CE equipment, embedded computers and netbooks.”
Intel's IEDM papers will also describe a low power system on the chip version of the company's 45nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45nm transistors, as well as integrating chemical mechanical polish for the 45nm node and beyond. In addition, Intel is also set to take part in a short course on 22nm CMOS Technology.