14 DAY TRIAL // It is true that the more advanced a nanotech-based production process becomes, the better semiconductors get, and thus, CPUs become faster and solid state memory gains more storage and efficiency. However, problems arise more and more as well, as we're about to see.
Though technically we have already seen it. Ever since 2010, when TSMC revealed just how poor the yields were for 40nm chips, we have kept seeing it.
We have reached the stage where Moore's Law has started to take a beating. While it states that the number of transistors on an integrated circuit has to double every two years or so, inexpensively, it has been getting hard to pull it off.
Production capacity is being hit by how many defective chips are yielded per wafer. TSMC is feeling it even now, at 28nm and 16nm.
And since it is more relevant to the topic of this article, Intel is experiencing it on the 14nm process as well, although to be fair, so is Samsung. And everyone else who is making any sort of chip with that node size.
Because of this, it will take longer to move from 16nm to 14nm. One year longer than some might like actually.
No 10nm chips until 2017
Taha Khalifa, Intel’s general manager for the Middle East and North Africa region, has just revealed as much.
That means that with the 14nm Skylake parts set for the second half of 2015, the new generation will last for three years.
That means one half 2015, the full 2016, one half 2017, and probably another year or so while 10nm gets its feet under it after that. This is similar to how the 22nm generation has been around for three years by this point.
Interestingly, 14nm is already two years late, since it never got launched in later 2013 as originally intended. Broadwell took a long time to finally show.
The 10nm processors will be called Cannonlake
These processors will have more in common with SoCs (system-on-chip devices), more than any Intel CPU to date actually, with coherent physical memory addresses and a more capable set of heterogeneous computing (CPU + GPU instruction sets). Unfortunately, no details exist right now.