14 DAY TRIAL // Most of you have probably seen the Barcelona presentation and know where the upcoming AMD CPU will fit in the roadmaps. Well, it seems that more good news emerge from AMD?s camp but not on the official channels. And all these ?rumors? (which I hope will come out to be true) are about Barcelona.
Barcelona will take many forms ranging from the native quad cores codenamed Agena (which will probably work on 1207 pin design) to some native quad core and dual core parts that will work on the existing AM2 socket but also on AM2+(HT 3.0 link) and AM3 (DDR3 support with future revisions of the integrated memory controller). According to the rumors coming from various Asian websites, the single-way Barcelona core will work at 1.9-2.0GHz in 68W TDP form, 2.1-2.3 in 95W TPD and 2.4-2.5 carrying a maximum of 120W TDP. Level 2 Cache is 512K * 4 + 2M of shared L3 resulting in a total of 4MB. That?s not bad but it still lags behind Kentsfield?s 8MB of total cache.
The hypothetical roadmap also suggests that 2-way and 8-way 1207 pins CPUs will be developed from the same Barcelona based design but they will be multi-CPU enabled. What?s odd about these CPUs is that they will only support about 2000MB/s of data bandwidth through the HT link which translates into the fact that they will only work with HT 2.0 standard instead of the updated 3.0 one. And yet another spicy detail: the HT speed of the future single-way Barcelonas should go higher than the standard 4000MB/s. The roadmap suggests a theoretical throughput of 5200MB/s. And that can either mean that the HT multiplier will be a number higher than 5 or that the base frequency of the HT bus may climb to 266MHz (533 effective).