14 DAY TRIAL // In addition to detailing a pair of upcoming Zacate APUs, reports have begun to speak of AMD's server processors, especially the 8-core Orochi chip, which may turn out to have more cache memory than some would expect.
Apparently, in order to significantly boost the performance of its server chips compared to the current generation, AMD will design the Orochi with a massive internal cache system.
This product will cater to the needs of both server and high-end desktop markets and will have its 8 processing engines packed inside four modules.
Each module will have dedicated schedulers, two integer cores that share L2 functionality and all four will share the same 8MB L3 cache.
The part will also integrate the DDR3 memory controller and utilize HyperTransport 3.1 bus, though it has one so-called disadvantage.
Basically, it will be compatible with the AM3+ socket, meaning that those companies interested in it will also have to purchase new platforms.
This processor will power Valencia and Zambezi first-generation Bulldozer systems and will have 8 MB of unified L3 cache, according to a report made by X-bit Labs.
Now, it seems that each of Orochi's 8 cores will boast its very own 2MB of cache, leading to a total of 16MB of SRAM.
In other words, the Orochi 8-core server microprocessor will have 77% more L2 cache than existing six-core AMD chips, which are limited to 9 MB.
All in all, a larger l2 cache will definitely lead to a higher single-threaded performance than what todays chips with 512 KB of L2 can brag about.
Finally, large L3 cache will optimize memory bandwidth, basically hinting at the fact that, together with the l2 cache, it will give CPUs a vastly superior performance to the parts AMD is selling right now.
Predictably, Advanced Micro Devices did not comment on this story in any way.