Erratum - Buzzword for when people screw it up

Dec 6, 2007 11:18 GMT  ·  By

The so-called microcode injection patch that was supposed to miraculously heal the Phenoms' faulty behaviour at speeds exceeding 2.4 GHz is a fiasco. It is true that it fixes the issue and the users will never experience system freeze on high overload again, but they won't experience high speeds either. All this due to a small yet obsessively repeated word: erratum. We will try to explain without much buzz what this erratum means and how this impacts over the processor.

The erratum, also known as Intel's F00F bug, has been documented since the official launch back in November and causes a hardware deadlock when the system runs at high capacity and recursive or nested cache writes occurs. Internal AMD conventions name this issue errata number 298, but since it involves the chip's translation lookaside buffer (TLB), specialists refer to it as the TLB erratum.

All the processors in the AMD quad-core line feature a shared L3 cache and there are instances when the software uses nested memory pages, which will induce the processor a race condition. This condition occurs when the memory arbiter is instructed to overwrite an older block of memory, but write the old block of memory somewhere else in cache. This is logical and prevents data loss, but when two arbiters attempt at writing the same blocks of information (since they follow the same ruleset), the system ends up hanging. More plasticly, AMD's desktop product marketing manager Michael Saucier defines "race" as the process when "the winner is the guy who isn't supposed to win". The AMD engineers say that the situation resembles virtualized machines that are using nested memory pages.

The microcode patch AMD has issued for all the K10 motherboards is supposed to alleviate the situation by tampering with the performance factor, not completely fixing it, because it just can not be fixed by software. The patch would just prevent the processor from ever running at full-speed. The bug not only affects Phenoms, but Barcelonas as well, and the company has canceled all the Barcelona shipments. Corporate customers can use Revision F3 (K8) processors for their equipments until the issue is completely solved.

AMD has estimated that the issue will be totally fixed in the next revision, called the B3 stepping. Both processor lines, Barcelona and Phenom, will get erratum-free, but not until March, when the B3 stepping has been planed. The 2.6 GHz processor, Phenom 9900, is likely to be shipped bearing the B3-stepping designation directly.