14 DAY TRIAL // Advanced Micro Devices, better known as AMD, announced in a press release its plans to further expand and upgrade the instruction sets that are implemented into its processors. While all x86 compatible processors are sharing a common instruction set that makes them compatible, every manufacturer introduced one or more extensions in order to expand functionality and improve performance in certain areas like floating point operation, multimedia processing or energy saving.
While the number of instruction sets developed and implemented by AMD is smaller than the one implemented by Intel on its products, the balance is about to get even as the Sunnyvale company decided to expand the functionality of its processors by adding a set of instructions named SSE5. This new addition to the hardware based instruction sets is intended to help software developers write simplified code that runs with greater efficiency and to improve overall performance in all applications including high performance computing, multimedia and security applications. As a new instruction set is virtually useless if software developers ignore it, AMD decided to make public technical specifications from the SSE5 set in order to increase its adoption before the implementing hardware platform is released.
"Chip advancements and software improvements go hand-in-hand, to the benefit of consumers and enterprises alike," said Phil Hester, senior vice president and chief technology officer, AMD. "The impact of our designs are best realized when AMD-based servers, PCs and devices enable software to more effectively solve every-day problems and enhance every-day experiences. By announcing our plans to add SSE5 instructions to the x86 instruction set ?? and by making the specification available today ?? we are enabling open and collaborative software innovation that will bring AMD?fs advancements to life for our customers and end-users." Coming in the form of 47 base instructions and expanding to a total of 170 hardware based instructions, the SSE5 set will first be included in the "Bulldozer" processor family, scheduled to be released in 2009. The SSE5 set comes as the continuation of the already announced initiatives to improve the company's multicore technology and overall performance such as the Lightweight Profiling Proposal, but unlike the other initiatives, the instruction set will directly benefit customers that are interested in running multimedia and security applications.
Because increasing the running speeds of most processors while still being power efficient is not possible with current designs and technologies, AMD is focusing on designing smarter processors that can outperform the competition at lower clock speed by introducing a number of innovations. SSE5 brings a number of new things to the internal workings of AMD processors like the 3-operand instructions which increases the number of operands from 2 to 3 resulting in a more efficient instruction and a closing in to the RISC architecture. Another improvement that comes with the SSE5, Streaming SIMD Extensions, is the Fused Multiply Accumulate instruction which enables multiplication and addition based calculations to be done iterative with just one instruction which according to AMD leads to "the simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications".