14 DAY TRIAL // Simply RISC is a joint Italian-English team of Open Source engineers responsible for a few 64-bit processor designs which are offered for free on their website - no registration required. The generous collective also develops peripherals and electronic interfaces released under GNU General Public License.
The S1 Core (codenamed Sirocco) is a simplified version of the OpenSPARC T1 multicore CPU (codenamed Niagara) designed for embedded devices such as PDAs or professional digital cameras. The S1 model is based on one 64-bit SPARC core and its designers integrated a Wishbone-compliant bus, a reset controller and a basic interrupt controller in order to facilitate easy interoperability with other multicore CPUs which can be found on the OpenCores website. S1 Core is able to execute four concurrent threads and UNIX/Linux distributions will detect a quad core array, even though the chip features only one core.
The Simply RISC team states that one of their main purposes was to keep a simple environment for the S1 Core, which would encourage software developers. They simplified most of the simulation and synthesis activities and developed push-button scripts, making system requirements easy to be met. S1 Core is compatible with any Unix/Linux distribution, making commercial tools redundant. The multicore CPU is also designed to work with Icarus Verilog free development software.
Simply RISC promises to add new features to the S1 Core and expects extensive testing with the aid and support of the GNU community.