14 DAY TRIAL // Rambus is to announce on Wednesday their Terabyte Bandwidth Initiative (TBI) that is supposed to raise the memory bandwidth to one terabyte for multiple-core systems. This speed could be achieved by using 16 DRAM channels able to transfer 14 Gbps with 4 bytes clock data. Summing up, this would result in a total amount of 1 terabyte split on 16 channels that would fuel a multi-core processor.
The bad news is that Rambus has not yet managed to go past theory. Although the technology is working at full speed the Rambus engineers could not integrate it into a functioning prototype. For demonstrative purposes, the memory has been tested on a testbed-machine using a generic 65 nm process technology which operates on a single channel at 64 GB/s. The machine specifications have not been disclosed yet and will be released by Rambus on November 28 at the Rambus Developer Forum in Japan.
The 16 Gbps pulse frequencies per channel is achieved using on-chip PLL-based FlexLink clocking systems. The input clock modulated at 500 MHz is injected through a PLL to achieve the 32x frequency at a maximum transfer rate of 64 GB/s, while moving to Fully Differential Memory Architecture (FDMA). The DDR3 technology uses only differential on the clock.
TBI will also feature a refurbished Command / Address bus totally different as the legacy, 12-line connection from memory controller to DRAM. The new technology will be using a 2-line connection that pushes data 32 times an input clock, but the frequency can be adjusted accordingly, if necessary.
The new technology will be capable of providing enhanced support for multiple types of granularity (the amount of memory retrieved for each query, no less than 16 bytes - usually between 64 and 128 bytes). Having supplemented the amount of bandwidth on the 32x link would allow a diminished granularity without affecting the system's latency.