The new single exposure lithography process offers cost-effectiveness and increases density

Dec 18, 2008 08:30 GMT  ·  By

Toshiba Corporation announced today its higher density 32nm CMOS platform technology able to provide improved performance at only half the cost per function that is available with the 45nm technology. The company revealed that the new platform was developed through the application of advanced single exposure lithography and gate-first metal gate/high-K process technology. According to the company's announcement, the technology can enable a 0.124μm2 SRAM cell and a gate density of 3,650 gate/mm2.

Moreover, the SRAM cell is said to be the smallest ever achieved in the 32nm generation. Toshiba also stated that the new technology based on the 32nm process had been jointly developed with NEC Electronics Corporation. The technological optimizations in lithography and patterning integration, device design and materials come as a need for cost competitiveness and enhanced performance driven by the advanced semiconductor process migration.

The company explained that its architecture was based “on single exposure lithography by applying ArF immersion lithography with a NA 1.3 and over, and by optimizing the lithography illumination conditions.” This process is different from the one originally used, which implies dual exposure technology in the lithography process. This drove higher costs as the process steps were more numerous, while increased process dusts resulted in degraded manufacturing yields.

According to Toshiba, the development of the new technology also proved that the application of a metal gate/high-K could diminish threshold voltage mismatch, in addition to boosting transistor performance, which offers more stability to SRAM and logic circuits operation. Moreover, the layout optimization of a bent-shaped type cell demonstrated reduced threshold voltage mismatch.

The 32nm CMOS platform design Toshiba developed through this approach is able to reduce cost per function by 50 percent from the 45nm technology, a result almost impossible to achieve with conventional poly/SiON and double patterning. The company also unveiled its plans to make further enhancements to the new platform.