14 DAY TRIAL // While the Taiwan Semiconductor Manufacturing Company has gotten over the yield issues related to its 40nm manufacturing process, it seems that not all the problems are over. After a recent rumor suggested that TSMC would only get over the last of its difficulties by the middle of the year, EETimes has now revealed the exact nature of these issues. The new report also unveils part of TSMC's plans for not only the 40nm, but also the 22nm process.
Initially, TSMC had to use new tools and materials to produce the 40nm wafers, which led to yields that were below original expectations. This problem, TSMC claims, is now past, but 40nm is still in insufficient supply. The reason for this, however, is not yield-related, but caused by the lack of equipment or, to put it simply, a 40nm demand too strong for the manufacturer's current equipment to meet. Still, the company hopes to double its capacity to produce 40nm wafers by the end of the year.
“Moving to 45nm and 40nm nanometer is a lot more challenging. This is the first time we began to use 193nm shrink immersion. That means the photo resist during exposure will be merged in water and is a very high potential defect. For this a very big challenge. We began to develop the third generation. We began to use the second generation low k material with a k value of 2.5 and at this k value the material become quite fragile so there is a lot of potential issues in the package side,” Shang-Yi Chiang, senior vice president of R&D at TSMC, said at the TSMC Japan Executive Forum in Yokohama.
“At this stage we only have fab 12 ready to tape production of 40nm and we are able to do about 80 000 wafers per quarter at the moment. These are 300mm wafers. And this will be doubled by the end of this year, to 160 000 300mm wafers for 40nm capacity by the end of this year, and partly from fab 12 and partly from fab 14,” Mr. Chiang noted.
Besides the 40nm manufacturing process, TSMC also intends to introduce 28nm products by the end of September. Initially, there will be a 28nm SiON/Poly process, aimed at low-power devices, with a high-k metal gate (HKMG) technology set to debut later on. The company will focus on this technology, instead of the 32nm, and also intends to tap into the 22nm process by 2012.
“The first node we are going to release for the 28nm will be called the 28LP. This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year, about four months from now, and this is for the low power application. […] The first HKMG process we call 28HP for the high performance application will be introduced by the end of September this year, and followed by three months later December will be the 28HPL, which is [our] first high-k metal gate introduction for the low power application,” Mr. Chiang explained.
“Going forward, we plan to introduce 22nm node about two years after we introduce 28nm. The first introduction would likely be in the Q3 of 2012 for the high performance version and followed by the low power version in about the end of Q1 2013. Going to 22nm and beyond, we would like two models to be introduced. Firstly, we will go to the second generation high-k metal gate. We will continue using the 193nm immersion with double patterning in the early stage, and [secondly] we will migrate to EUV or multiple e-beam direct write if one of these technologies can be more mature and more cost effective.”
In the meantime, TSMC will have to make sure that its yields, performance and services are better than those provided by its main rival, namely Globalfoundries.