14 DAY TRIAL // Transistors work in binary, with their states being interpreted as 1 and 0 by software. It is the transistor number and the speed at which they switch between states that determine performance. There is only so much that planar transistors can do, however, which is why IBM has been researching new ways to make 3D ones.
Central processing units (CPUs), graphics processing units, all kinds of integrated circuits really, had one thing in common until 2011: they all used planar transistors.
In planar projection, a circuit is viewed in its two-dimensional projection, which allows photographic processing concepts (like a film negative) to mask the projection of light-exposed chemicals.
This, in turn, makes it possible to use a series of exposures on a substrate (the silicon) to create silicon oxide (insulators) or doped regions (conductors).
With the added contribution of metallization, the integrated circuits are joined together and the concept of p–n junction isolation is applied next, to create circuits on a single silicon crystal slice from a monocrystalline silicon boule.
How 3D transistors are made
In regular terms, silicon wafers are coated with a light-sensitive material (photoresist) and exposed to a pattern made by shining light through a filter (the mask).
The photoresist cures (hardens) where the light strikes, allowing the rest to wash away. The resulting wafer is etched chemically to create features in exposed parts of the surface.
This process is repeated 30 times on 22nm CPUs (with 80 nm distances between elements) and each step needs a new mask (which is expensive).
Unfortunately, this means that small chips will cost increasingly more, until the limits imposed by light wavelength are finally hit.
IBM has found a new way to create them
3D transistors switch faster while consuming less power than planar ones, so there is no way they will be set aside. But the current way to make them won't be worth using beyond the upcoming 14nm die shrink, so a new method was needed.
IBM's technique uses block copolymers (polymer chains are made up of two kinds of monomers / blocks) to perform “directed self-assembly.”
Here, direct control over the polymer length, size, interaction (how blocks attract and repel) allows for the materials to assemble themselves into complex patterns at the molecular level.
These patterns can be much denser than using lithography, but they are meant to complement it, not replace.
To prove it, IBM created a photoresist coating with a series of deep, parallel trenches via existing photolithography. Then it used the trenches to direct the assembly of block copolymers.
Those were then arranged in patterns needed to etch much smaller and densely packed transistor fins than would otherwise be possible.
This allowed for chips to have features 29 nm close to each other, a great progress compared to the 80 nm limit currently in play.
Practical applications
The new 3D transistor creation method can be applied to all integrated circuits (CPUs, GPU, SSD controllers, network controllers, I/O controllers, etc.) and is already being tested by some chip makers. Unfortunately, copolymers assemble with defects at present, so the process needs to gain a higher degree of control before anything comes of it.