Sub-Nanometer Scale Pore Structures Imaged

Years ago, when Moore's Law first appeared, it predicted that the number of transistors that will be fitted on a computer microprocessor will be doubled once every couple of years. The trick is to do so inexpensively and constantly, and modern technology is beginning to reach the limits of transistor miniaturization. New options of continuing forward are being sought for, while some groups continue to work in the traditional method. One such group is based at the Cornell University, in Ithaca, New York, and researchers here recently managed an impressive breakthrough – they were able to image pore structures at sub-nanometer scale, inside insulation materials.

Gaining a better understanding of how these structures form and act, the scientists say, could allow for the creation of more advanced computers, with increased performance levels and that consume energy more efficiently. The work was carried out in collaboration with experts from the Semiconductor Research Corporation (SRC). Generally, the group explains, silicon dioxide was used as the insulator material between copper wire. But the newest choice is represented by very porous, low-dielectric constant materials, which are more efficient at this job. The copper wires themselves have shrunk to the nanoscale with the passing of time as well.

When the new materials began being used, the speed of the electrical signals passing through the nanoscale copper wired increased, while the entire system reduced its overall power consumption. “Knowing how many of the molecule-sized voids in the carefully-engineered Swiss cheese survive in an actual device will greatly affect future designs of integrated circuits. The techniques we developed look deeply, as well as in and around the structures, to give a much clearer picture so complex processing and integration issues can be addressed,” says the co-director of the Cornell Kavli Institute for Nanoscale Science, professor of applied and engineering physics David Muller.

The new imaging method the collaboration develops draws on techniques commonly used in the medical world, such as CT scans and MRI investigations. “Sophisticated software extracts 3D images from a series of 2D images taken at multiple angles. A 2D picture is worth a thousand words, but a 3D image at near atomic resolution gives the semiconductor industry new insights into scaling low-k materials for several additional technology nodes,” explains the director of the SRC Interconnect and Packaging Sciences, Scott List. Details of the accomplishment appear in the June 2 issue of the esteemed scientific journal Applied Physics Letters, in a paper entitled “Three-dimensional imaging of pore structures inside low-κ dielectrics.”