14 DAY TRIAL // Intel has been working on what is the so-called first high-performance computing (HPC) accelerator, one that is supposedly based on the Larrabee GPU design, and it seems that its first public demonstration has taken place.
What Intel showed off, or so reports have it, were the so-called 'real-world capabilities' of the many Intel core (MIC) architecture, represented by the Knights Ferry device.
The event which acted as the staging ground for this demo was the SC10 trade-show that focuses on supercomputers.
Intel chose, as an example and so-called testing platform, an MIC architecture-based chip as a co-processor running financial derivative Monte Carlo demonstrations.
Said Monte Carlo application was generated using standard C++ code with a special version of the Intel Parallel Studio XE 2011 software development tools.
By special version, one means that said version of the software development tools had been modified in order to become compatible with the Intel MIC architecture itself.
Apparently, the chip was able to pull off a performance twice as good than that displayed by previous-generation technologies.
Unfortunately, the Santa Clara, California-based chip giant did the same as before and held off on actually providing numbers.
What this means is that no raw computing performance was disclosed, meaning that the amount of GigaFLOPS or TeraFLOPS Knights Ferry can deliver is still a mystery.
On the other hand, some details on the hardware itself were provided, and it seems that Knights Ferry has 32 x86 cores, each of which has a clock speed of 1.2GHz.
The most interesting element, one might say, of this development platform is the 8 MB L2 cache memory itself, as it is larger than what highly-parallel applications actually need.
Other specifications include quad-HyperThreading and up to 2 GB of GDDR5 memory, plus a design that lets it be placed inside PCI Express 2.0 slots.