Rambus and Kingston Collaborate on the Development of Threaded Module Prototype

In an attempt to provide the IT market with a boost of performance for notebook, desktop and server systems, Rambus and Kingston Technology have announced today a partnership for the development of a threaded module prototype that takes advantage of the specifications of DDR3 DRAM technology. According to a recent press statement, initial silicon results of the new solution show an improvement of 50 percent in data throughput, while the overall power consumption can be reduced by 20 percent when compared to conventional modules.

“As multi-core computing becomes pervasive, DRAM memory subsystems will be severely challenged to deliver the data throughput required,” said Craig Hampel, Rambus Fellow. “Our innovative module threading technology employs parallelism to deliver the higher memory bandwidth needed for multi-core systems while reducing overall power consumption.”

The use of the threaded memory module technology is said to present several benefits for today's memory module devices, including boost of performance and the reduction of the energy consumption. The two companies claim that, by partitioning the modules into multiple independent channels, with a shared command/address port, memory solutions can deliver a boost in the system's power efficiency.

“Kingston is at the forefront of memory technology working closely with innovators like Rambus to develop advanced solutions,” said Dr. Ramon Co, vice president of Worldwide Test Engineering at Kingston Technology. “The collaboration of our experienced teams produced a memory solution that helps overcome a major challenge with multi-core computing.”

The technology can enable modules that support 64-byte memory transfers with full bus utilization, which translates into efficiency gains of up to 50 percent compared to current DDR3 memory modules. In addition, the same technology enables the drives to be activated half as often as in conventional modules, which means that they will provide a 20 percent reduction in overall module power.

A demonstration of the new prototype will be showcased at the upcoming Intel Developer Forum (IDF) event, which will be held between September 22-24, 2009, at the Moscone West in San Francisco, California.