PCI Express 3.0 Specification Bound for November

Apparently, the current PCI Express specification is no longer enough for the PCI special interest group (PCI SIG), who have been diligently working on the new specification, version 3.0 to be exact, set to debut two months from now.

Earlier this year, the organization said it would start testing prototypes of PCI Express 3.0 products in 2011.

Also, the 0.9 version of the new PCI Express link was revealed in the middle of August, with its full range of new features and better transfer rate.

The third generation of PCI Express will run at 8.0GT/s (8.0GHz) and will move 128-bit and 130-bit encoding schemes.

There are already two extensions for this technology, proposed by Advanced Micro Devices and Hewlett Packard back in 2008.

One of them is called lightweight notification and allows co-processors or peripheral chips to intercommunicate through the system memory.

This communication is done through a PCIe transaction, without interrupting said host processor.

The other extension is protocol multiplexing, a feature that lets chips dynamically switch between seven distinct protocols besides just PCIe, using a shared set of pins.

This would enable the creation of chips compatible with HyperTransport, PCIe, QuickPatch Interconnect, Ethernet and other buses at once.

The first companies to implement the PCI Express 3.0 interface will be makers of solid state drives (SSDs), Infiniband interconnects, high-end video boards and 100Gb and 40Gb Ethernet cards.

Not only that, but even Intel has supposedly started to implement this new high-speed interconnection into its Sandy bridge central processing units.

Nevertheless, though the specification itself will be done by November, a specification for testing PCIe 3.0 products won't be ready until late 2012, which means that tools to validate designs will be released in the middle of next year at the earliest.

Interoperability workshops will, likewise, only be set up around the middle of 2011.