The gigahertz battle was abandoned by AMD and Intel a couple of years ago with the introduction of multi core CPU architectures. Nevertheless, IBM continues to be an important player on the CPU market, aiming not only at developing efficient multi-core CPUs, but also clocking its processors as high as possible.

IBM has recently unveiled its Power 6 processors to key partners worldwide. The multi-core CPU will be clocked between 4 and 5GHz, as each SMT2 core would be accessing 4MB of L2 memory and an additional 32MB level three cache.

Technical information on the new IBM CPU reveals that the new architecture will greatly improve the performance of dedicated servers. Thus, a Power 6 CPU can access data at 64B/2 cycles at Level One cache, while the L2 bandwidth is capable of 127B/5 cycles per core. Now, as you may already know, IBM is known for its flawless micro-architectures and the SMT2 cores once again reiterate this fact. This way, a dual core Power 6 CPU will have nine execution units per core, with 790 million transistors on a 341 square millimeter die. Further specs reveal that the new processors integrate a seven way superscalar design built on SOI 65nm process and feature two memory controllers per core.

Big Blue plans to offer customized versions of the Power 6 CPU, swapping cache depending on what customers demand for their specific system configurations. Estimating a 30% performance boost over the previous 90nm chips, IBM claims that the latest CPUs perform better with the aid of the newly-introduced SRAM cells. Including server-grade CPUs, the Power 6 series will feature nine execution units and will drastically reduce logic stages per cycle to allow for higher frequencies. As an added bonus, the all-new set of 54 instructions will include added arithmetic, comparison, test, convert, format and quantum adjustment variables for extended performance.