A group of investigators at the IBM Watson Research Center in Yorktown Heights, New York, announce the creation of the world's smallest carbon nanotube transistors, a device that measures only 9 nanometers across. That is the equivalent of 9 billionths of a meter.
As the drive towards miniaturizing electronics even further continues, physicists are starting to come up against obstacles that they never thought of before. In order to circumvent them, they started a search for a material capable of replacing silicon, and carbon is now apparently the leading candidate.
It is currently starting to become clear that silicon is beginning to reach its limits. Beyond certain levels of miniaturization, the material loses some of its capabilities, making further downscaling impossible.
The new CNT transistor is not plagued by this problem. A study shows that it performs a lot better at even the smallest dimensions than the most advanced silicon transistors of the same size and function.
Though researchers proposed replacing silicon with far-superior carbon many years ago, the technical means to test whether this is possible at the smallest scales have been lacking until now. This research constitutes an important proof-of-concept in this direction.
“The results really highlight the value of nanotubes in the most sophisticated type of transistors. They suggest, very clearly, that nanotubes have the potential for doing something truly competitive with, or complementary to, silicon,” University of Illinois in Urbana-Champaign (UIUC) professor of materials science John Rogers explains.
The IBM team behind the study says that this is the first set of experimental evidences to suggest that silicon can be replaced by carbon at scales lower than 10 nanometers. The new transistors allow more current through, and need less power to operate than their silicon-based counterparts.
WRC researcher Aaron Franklin says that one of the problems the team has to deal with now is figuring out how to synthesize pure batches of semiconducting nanotubes in a cost-efficient manner. An additional challenge is developing a technique for aligning the new transistors on a substrate, with near-perfect accuracy.
The latter is absolutely essential if the new transistors are to be included in advanced processors that maintain their current sizes. This, too, may not be enough, since the trend is to miniaturize chips further, not increase their sizes again .
Details of the new study appear in the latest issue of the esteemed journal Nano Letters
, which is published by the American Chemical Society, Technology Review