NEC to Diminish the Design Time of Large ASICS

NEC said it has developed a new semiconductor design technique - the "border moving method" into the design process in order to diminish the design time of large Application-Specific Integrated Circuits (ASICS) with more than 50 million transistors. "This can eliminate the need for the budgeting process and re-designing of hierarchical blocks, dramatically shortening the total length of time required for backend design for large scale and high speed LSI to 1/3 of the conventional design method," said the company.

More precisely, an ASIC is an integrated circuit which has been previously modified in order to fit the requirements of a particular product/use. "For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together to perform many different applications. Intermediate between ASICs and standard products are application specific standard products (ASSPs)," explains Wikipedia.

NEC officials explained the way in which the design blocks are manufactured. It seems that it is much too hard for the designers to handle the entire design, as it could require more instruments than the ones already in use.

Consequently, the most popular method is the one named "hierarchical design method", which consists of partitioning the design into several hierarchical blocks which are then 'planned' independently and assembled at the end of the process into one IC. The sole issue regarding this technique is the budgeting that is made in order to determine a timing restriction on a signal path between two hierarchical blocks.

"With the NEC approach after designing hierarchical blocks, the method modifies the boundary of blocks and moves partial signal paths out of the blocks. These partial signal paths, which used to reside inside the blocks, and the partial signal path connecting the blocks are then combined into one signal path. As a result, only the delay for the single signal path has to be considered, eliminating the need for budgeting and re-designing hierarchical blocks," explains Electronics Weekly.