Slated to be released in the third quarter of this year, Intel's Sandy Bridge EP processors will feature as much as 40 PCI Express 3.0 lanes as well as a special memory controller design that changes the operating speed of the DDR3 modules according to the number of DIMMS installed.
These new processors will be based on the architectural changes introduced by Intel with its Sandy Bridge CPUs and feature improved IPC as well as lower power consumption.
Destined to make their way into 1-way and 2-way servers, Sandy Bridge-EP CPUs use the LGA 2011 socket and the recently leaked
Patsburg chipset.
As far as the number of available cores go,
Intel plans to release quad, six and octo-core models, all the SKUs featuring Hyper-Threading support.
This effectively doubles the number of threads available to the operating system, making them particularly well suited for running highly parallel applications.
However, as SemiAccurate has uncovered, the high thread count will also be accompanied by a fair amount of PCI Express lanes, the website suggesting that as much as 40 lanes worth of PCI Express 3.0 bandwidth are available from the CPU.
This fact is important since it allows system manufacturers to install high-performance interface cards or multiple graphics cards.
Furthermore,
SemiAccurate also points out that LGA 2011 will vary memory speeds depending on the number of modules that are fitted in each channel.
The highest performance is achieved when one DIMM per channel is used, as the memory will run at a full 1600MHz.
Installing two DIMMs per channel will drop the memory speed down to DDR3 1333MHz speeds, while using three modules per channel brings this further down, to 1066MHz.
Together with the LGA 2011 Sandy Bridge EP, Intel plans to introduce the
Sandy Bridge EN processor line that features triple-channel memory support and uses the LGA 1356 platform.
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