Micron and JEDEC Want to Standardize 3D DRAM Chips

Micron has been working with both Intel and IBM on 3D memory chips and, now, the company has begun a close collaboration with JEDEC for the standardization of the 3DS DRAM interface and die-stacking technology.

JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council (JEDEC), may give Micron all the help it needs to promote its latest pet project.

Said project is the 3DS, a memory chip stacking technology that places DRAMs on top of each other, creating 3D chips (hence the name).

Such chips have a single, master die interfacing with the external memory controller and use optimized DRAM, single DLL per stack and reduced active logic.

3DS also boasts a single, shared external I/O, plus improved timing and reduced load to the external world.

All in all, 3DS memory should possess better timings, bus speeds, signal integrity and a lower power consumption to boot.

Future-generation modules will definitely make waves once they start to call on this technological advancement, assuming customers actually start to show interest in memory.

Right now, memory is selling so poorly that 4GB DDR3 RAM Modules Sell for Just $16.5 (12.65 Euro).

Through collaboration with JEDEC, Micron's 3DS may end up at the forefront of the DDR4 generation.

That won't happen for a few years, though, so the memory segment may turn around by then.

In the meantime, some may be interested in the demo video where the company explains how the 3DS is not plagued by the one-cycle gap on the data bus that normal DRAMs show when reading from one rank and then passing to another.

“In the second case, we are observing how data is continuous when the system issues consecutive Read commands on the same rank. A 3DS-optimized system will similarly take advantage of this tighter timing and be able to see improved data bus utilization and bandwidth when reading from different banks,” said Aftab Farooqi of Micron Technology.