Mentor Graphics Collaborates with ARM on New Designs

Mentor Graphics deals in electronic design automation, and its recent projects have come to involve a closer partnership with ARM, so that processor-based designs may be more easily created.

Computer-aided design automation is a very important part of the global IT industry, since it is used in more or less everything nowadays, in some measure.

Mentor Graphics has always been in the thick of it, so it was not overly shocking to learn that it has stepped up its efforts involving ARM chips.

What the latest press release states is that Mentor and ARM co-developed a reference flow which, through documentation, scripts and seamless interfaces, accelerates development of complete test solutions for ARM intellectual property.

The flow is based on the Tessent test tools and can test cores and logic, plus embedded memories used in customer SoCs.

“Our joint effort with ARM is extremely beneficial for our mutual customers because it enhances the time-to-market advantages of using ARM IP by helping them achieve their testing objectives in the least amount of time,” said Steve Pateras, product marketing director, Silicon Test Products, Mentor Graphics.

“The Tessent solution also helps the bottom line with the most efficient testing available to reduce test time and overall manufacturing cost.”

The reference flow is named Tessent TestKompress and defines all necessary steps for incorporating and verifying test compression and memory BIST IP.

It also generates all necessary test patterns and supports self-repair technologies inherent in BIST memory.

“The new Tessent TestKompress reference flow provides our customers with a simple and verified test methodology for cost-effective, high quality test of processor cores and associated logic,” said Teresa McLaurin, DFT manager at ARM.

“This builds on our previous collaboration on comprehensive, automated built-in self test (BIST) solutions for ARM physical memory IP using the Tessent MemoryBIST product.”