MAIA EDA Releases Automated Functional Verification Tool

Normally, when hardware engineers write their own RTL code, they also have to put together a manually created testbench meant to verify it. This task is dreadfully time-consuming and, more often than not, errors manage to slip through, leading to imperfect or incomplete testbenches. The MAIA Automated Verification tool is capable of generating such complex self-testing reactive testbenches based on the description of the evaluated device/module's expected behavior.

“Module verification is normally carried out by the same hardware engineer who designed the module. The engineer is expected to hand over a working module,” Evan Lavelle, CTO of Maia EDA, commented. “However, engineers are not usually programmers, and are unlikely to have the mindsets, or the time, which are required to create complex and exhaustive verification programs. The result is frequently that FPGAs are tested and debugged in-system, and ASIC developers have to buy complex system-level verification tools to find problems that should have been caught at a lower level. It's also a fact that most engineering companies don't have the resources to hire dedicated verification staff anyway. This is where Maia fits in.”

The tool not only frees up the time of engineers who write their own RTL code, but its key feature lies in its usability by staff members who have little programming skills and possess little to no Verilog or VHDL knowledge. The MAIA application specifies a so-called “solution” by listing vectors representing sequences of inputs and expected outputs. The vectors are then used as constraints in the subsequent creation of the self-checking testbench, which, after having reached its final stages, is used for the automatic evaluation of the respective device's various features.

“Maia treats the vectors as constraints, and creates the corresponding self-checking testbench, automating the processes of driving and testing timed device inputs and outputs, clock and reset generation, stability checking, pipeline handling, internal signal probing and forcing, time handling, and error reporting,” the press release said.

Maia uses declarative and fifth-generation language (5GL) techniques in the creation of its testbenches. The tool is currently being offered as a free trial without registration or risks and may be downloaded from the official website.