Processors will debut on the 16th of March, 2010

Dec 15, 2009 10:57 GMT  ·  By

Even the IT industry must be feeling the influence of the impending planetary alignment that will occur in 2012. Already, its effects have begun to show, as company leaks gravitate more and more towards the Internet, with docs detailing future releases even slipping away from the Santa Clara-based chip giant. The leaked document is an Intel product roadmap that includes a table listing the “Xeon 5600 sequence” set for release on March 16.

The table shows that 13 dual socket Xeon processors based on the 32nm manufacturing process will be launched on the aforementioned date, along with three Xeons based on the 45nm process. Six of the 32nm chips are Intel Xeon six-core processors, which all have a cache memory of 12MB and 12 threads (thanks to Hyper-Threading). The six processors will have clock speeds between 2.26GHz and 3.33GHz and will have a power consumption of either 60W, 95W or 130W.

The seven quad-core processors listed are based on the same 32nm manufacturing process and also boast 12MB of cache memory. Their clock speeds range between 1.86GHz and 3.46GHz and they have a power-consumption rate of between 40W and 130W. All of these quad-core processors are capable of HyperThreading and Turbo Boost technologies and each one boasts eight threads, except for the Xeon L5609.

Included in Intel's release plans for March 16 are also three quad-core processors based on the 45nm process. These units are notably inferior to the newer models, particularly through their cache memory, which only amounts to 4MB, or 8MB for the W3530. They use up 80W of power, except for the W3530, which consumes 130W, and have processing speeds that range between 2.00GHz and 2.80GHz.

The Intel S5520UR (Urbanna), S5520HC/S5500HCV (Hanlan Creek), S5500BC (Bluff Creek), S5500WB (Willowbrook) and S5520SC (Shady Cove) motherboards were also mentioned in the leaked document and were listed as compatible with the CPUs at launch.

The included table lists all CPU models and their respective clocks, power requirements, cache memory and the manufacturing process.