JEDEC Reveals Key DDR4 Details

JEDEC Solid State Technology Association has been working on the next DDR memory standard for months already, and it looks like it is ready to disclose some of the key features that users can expect from DDR4.

The DDR4 standard is scheduled to be published at some point during 2012, in the second or third quarter.

It will have both a higher performance level, as well as a significantly reduced power consumption.

So far, however, there has been little said about the specifics, but users can finally say goodbye to some of the guesswork, because, in a recent press release, JEDEC disclosed some of the key features of the upcoming standard.

The per-pin data rate, for instance, will be of 1.6 giga transfers per second, with 3.2 giga transfers per second to be reached later (higher standards are expected as well).

Th DQ bus will also have thee data width offerings (x6, x8 and x16), as well as data masking and overall better efficiency and bandwidth.

“Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption,” said Joe Macri, Chairman of JEDEC’s JC-42.3 Subcommittee for DRAM Memories.

“JEDEC invites all interested companies worldwide to participate in the development of DDR4. The next committee meeting will be held in Chicago in September, 2011.”

The VDDQ constant will be held at 1.2V, though the intent remains to keep reducing this VDD supply voltage.

Additionally, JEDEC expects to throw in differential signaling for the clock and strobes, as well as the ability to the DQ bus to shift termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.

Error detection capability during data transfers will also be provided, thanks to the new CRC for data bus (works even in non-ECC memory applications). Users can find more information here.