Intel's current desktop and laptop processors are built using a 45nm process technology, which enables the Santa Clara, California-based chip maker to create faster and more energy efficient computer processors. However, the company is expected to release next-generation chips, built using a 32nm process technology, which it could even detail at the International Electron Devices Meeting (IEDM), in mid-December 2008. The first 32nm-based chips were showcased back in 2007 but, at the time, the company did not specifically detail the process itself.

 

According to recent information, Intel is expected to unveil specifics of its 32nm chips at IEDM, although a document posted event-dedicated website already provides several details on the process.

 

Some of the features brought about by Intel's 32nm manufacturing process include the company's second-generation high-k/metal gate technology, a strained channel and nine levels of low-k interconnect dielectrics. According to the aforementioned paper, cited by EE Times, Intel built a functional 32nm, 291-Mbit SRAM array test chip with a cell size of 0.171-micron². The device could house nearly 2 billion transistors, and boasted and array density of 4.2-Mbit². Apparently, the chip managed to operate at 3.8GHz, at 1.1 Voltage.

 

The process is claimed to enable the highest drive currents reported to date for 32nm manufacturing technology.

 

The leading chip maker is said to be planning the commercialization of its 32nm process technology next year. The node will apparently allow the company to enter the market for ultra-low power x86 microprocessors designed for handsets. It will also enable Intel to design processors that come with a built-in graphics core, as well as higher-performance CPUs that can be offered at much more competitive price-points.

 

Given that it’s been a while since Intel first demonstrated the 32nm SRAM+logic test chips, this can only make users wonder if the company isn't already hammering away at working samples of 32nm-enabled microprocessors.