The cache design is radically different from any previous Intel architectures

Aug 29, 2012 11:28 GMT  ·  By

Built in the company’s 22nm manufacturing technology, the novel Many Intel Cores (MIC) architecture is apparently radically different from anything attempted before by the semiconductor giant. The current version of the architecture is called Knights Corner and the industry awaits the famous Xeon Phi cards based on it.

We reported on the latest development regarding the Xeon Phi accelerator cards here and we know that the whole processor will likely have 64 cores, while the Xeon Phi adapters will have some of these cores disabled.

Having so many computing cores on a chip requires a lot of coherence and synchronization work to be done internally to avoid stalls, collisions and generally high latencies.

When all instructions are perfectly optimized for a specific architecture, top performance can be achieved.

This never happens in reality, and a lot of prediction and prevention must take place to run things smoothly no matter how the computing stream varies.

This sort of problem is aggravated on a GPU, as these are massively in-order chips that require data to be similar and not vary too much. A modern CPU is best equipped for variable computing tasks as most have an out-of-order (OOO) architecture.

With MIC, Intel is going back to an in-order architecture and the problem of making all the cores collaborate efficiently is much more complex.

When communicating with each other, the cores inside Knights Corner use a ring BUS concept, but this is dramatically different from what many would remember.

Each of the cores inside the Xeon Phi has its own 512 KB of level 2 cache and this type of cache is set up differently.

There are several “rings” communicating between the cores, but unlike what Intel introduced with Nehalem, the level 2 cache of each core is private.

Therefore, there is no situation where a lightly threaded application would see four or eight of those cores benefit from the whole huge 32 MB of level 2 cache.

Considering that not all cores will be active, some would say that there won’t be so much cache present on the Xeon Phi. The reality is that, despite being deactivated, the cache is still there taking up die area and if cache in general is the criteria (all levels included), the Knights Corner will certainly have more than 32 MB.