Intel’s Crystalwell Technology Uses a Wide Memory BUS

We reported here on Haswell’s GT3 integrated graphics processing unit (iGPU) and, for those who don’t remember our spring report, we must say that Crystallwell technology is the so-called L4 cache that the new processor will come with.

The company clearly needs some sort of memory buffer for its iGPU, as this is the best way to ensure a performance increase besides increasing the number of shader units or the clock frequency.

In the case of GPUs, the graphics memory BUS width is the greatest performance bottleneck and hardware experts from Semiaccurate.com believe that Crystawell technology is reportedly a wide memory BUS design attempting to solve that issue.

It is very complicated to use eDRAM in such a manner and a big quantity of off-die SRAM is definitely out of the question.

The likely design will apparently look like a 512-bit-wide DRAM BUS that, in a low-power 1066 MHz implementation, will actually offer the same bandwidth as a 128-bit GDDR5 buffer running at a high 4GHz effective frequency.