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February 17th, 2011, 20:31 GMT · By

Intel Xeon Sandy Bridge-E Server Roadmap Revealed

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Intel Xeon Sandy Bridge-E server roadmap revealed
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A lot of details about Intel's upcoming Xeon server processors based on the Sandy Bridge-EN and Sandy Bridge-EP architectures have been revealed these last few months, and now a new slide detailing Intel's plans regarding the transition to the Xeon E5 line of processors comes to settle once and for all the company's plans regarding these new chips.

The roadmap was uncovered by the ComputerBase website, which has also posted online a slide detailing the naming scheme used by Intel's upcoming Xeon processors.

As most of us already guessed, the Sandy BridgeiEP series of CPUs will take the place of the present day Westmere-EP chips and is destined to be used in dual and quad socket LGA 2011 motherboards.

These processors will feature a quad-channel memory interface as well as 40 PCI Express 3.0 lanes which should be able to deliver an impressive bandwidth to the PCIe add-on cards installed.

The dual socket processors will be launched in the Xeon E5-2600 series while quad-socket compatible CPUs are going to be released under the E5-4600 designation.

Moving to the processors based on the Sandy Bridge-EN architecture, these will feature a tri-channel memory controller, similar to the one found in the current Nehalen-based Xeon processors.

The number of PCI Express lanes available has also been downgraded to 24, although they will still support the PCIe 3.0 stnadard.

These CPUs are to be released under the Xeon E5-2400 and E5-1400 brand names and are going to use the LGA1356 socket.

All Xeon E5 processors will use the C600 chipset, code-name Patsburg, that we detailed in a previous report.

Intel Xeon Sandy Bridge-E server roadmap
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Intel Xeon Sandy Bridge-E server naming scheme
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According to some recent leaks, Sandy Bridge-EN and Sandy Bridge-EP CPUs feature as much as eight processing cores, pack up to 20MB of shared L3 cache, have a TDP rated between 80W and 150W, and support one or two Quick Path Interconnect links, depending on the model.

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