The Tera-scale project is the latest multi core setup from Intel which is aimed at supercomputers and high performance servers. A prototype Tera-scale chip was built in February 2007 and it featured no less than 80 processing cores while being clocked at a total running frequency between 3.16GHz and 5.8Ghz. The prototype chip was built using the 65 nanometer fabrication process and when the Intel engineers ran benchmarking programs using the new multi core chip, results were remarkable as the system reached 1.01 Teraflops of parallel computing while using less power than a high-end widely available processor.

Consuming only 62W for 1.01 Teraflops, the Tera-scale was then ramped up to 1.63 Teraflops at 5.1 GHz and 175 watts and 1.81 Teraflops at 5.7 GHz and 265 watts, while using most of the shelf logic components and some pretty standard fabrication processes. Each processing core implemented a number of already developed and well established technologies for its internal architecture components like the arithmetic units, memory controllers, internal routing technology and caching. While a number of modifications and tweaks were necessary, the amount of changes needed was minimal according to the news site tgdaily. While the idea of muli core computing is nothing new and in fact it is widely used today, Intel was the first company to introduce such a large number of cores on a single computer chip.

In order to create the Tera-scale chip, Intel had to build a new communications system which would allow any core to "speak" to any other core and to the outside world. In order to achieve this stage Intel grouped the processing cores into nodes, eight cores for one node and each node is able to communicate with any other node or any other core. While internal core to core direct communication between the cores from a single node is possible, a core from a certain node uses the node to node protocol when the need to "talk" to an outside core arises. Apart from the core and node designs used by Intel, the processor manufacturing company also implemented a layered design for its Tera-scale prototype as the memory units sit at the very bottom of the die and on top of them there are the processing cores and nodes. For every core there is a dedicated amount of 64MB of RAM, so for the entire chip, 5.12GB of random access memory was used. Apart from this design specifications, Intel also used a reduced clock signal distribution system, which simply put, means that the Tera-scale uses around 10 percent of its power to synchronize the different clock frequencies, while conventional designs go as high as 30 percent.

Another impressive feature of the Intel Tera-scale project is the ability of the chip to self diagnose its cores and if one or more of them fail the self testing procedures they are simply marked as invalid and the system will continue its functions. From this self diagnosing ability also comes the ability to shift entire workloads from one core or node to another in order to make the most of the processing power available. Because the workload shifting is done at a hardware level, for the upper level, the software one, nothing has changed, not even the operating system being able to make the difference. As the Tera-scale project is still in the developing phase and because Intel plans to optimize the design even further, commercially available products featuring the Tera-scale design and technologies are still some years away, but according to one of the Intel engineers, servers might get processors using some or all the Tera-scale technologies as early as 2012.