14 DAY TRIAL // Old chips and any sort of degraded processor or system environment will eventually start showing signs of old age, meaning that performance will drop because of aging transistors, temperature changes or variations in supply voltage. According to Keith Brownman, Intel staff research scientist, such degradations have the potential of affecting the signal timing of chips. Normally, chip designers insert guardbands into the data flow in order to protect the chips from such timing issues, but the latest research from Intel, The Register reports, aims to reduce guardband use.
Intel seeks to reduce the use of guardbands because they waste energy and time, which, in microprocessor design, translates into a reduced throughput. The term “guardband” refers to a timing differential between clock signals and data inserted into the design in order to allow the signals to communicate without being perfectly aligned. This is necessary because signal rates can vary and the guardband acts as an “extra slice of time.” Browman and his team have now developed a chip with “resiliant and adaptive” circuits, based on EDS (embedded error-detection sequentials) and tunable replica circuits (TRC).
EDS and TRC work hand-in-hand and detect errors, replay them in order to get the correct results and tune clock speeds for less errors during operation. These technologies are not exactly new breakthroughs, but among the latest refinements made to them is a new recovery algorithm. If this error-control unit detects that the error frequency surpasses a certain limit, it will activate the adaptive clock controller in order to reduce the chip speed, until errors and replays decrease. This is useful because, in cases of a high error frequency, the chip is forced to replay many instructions.
"The key research contributions of this work lie in the error detection, the error-correction circuits, as well as the adaptive clock controller," Browman said. "For error detection, we implement error-detection sequentials on actual critical paths in the core. And then we introduce the first implementation where we use a tunable replica circuit combined with error recovery that allows us to detect both fast-changing and slow-changing dynamic variations."
Browman says that the total throughput increase they can achieve, when comparing resilient circuits to a conventional design, is of 41% if they lower the supply voltage of the conventional chip so that there is equal energy relative to the EDS and the TRC. This translates into a 22% energy reduction when they provide the conventional chip with enough power to match the throughput of the resilient circuits.
The technology was described on Tuesday at the International Solid-State Circuits Conference (ISSCC) in San Francisco.