Intel Haswell CPUs to Launch in Mar-Jun 2013, Says Leaked Company Roadmap
The chip maker's next-gen 22nm CPUs get an approximate release date
The launch date of Intel’s 2012 Haswell processors has so far been covered in mystery, but recently a leaked company roadmap has revealed that these chips are expected to arrive in the March-June timeframe.Just as it’s the case with the upcoming Ivy Bridge launch, the first CPUs to arrive will be introduced in the Core i5 and Core i7 product lines.
These will cover the mainstream and performance sector, while the lower end Core i3 processors are expected to be launched later that year, according to the info leaked by Donanim Haber.
Haswell will be a “Tock” on Intel’s roadmap, meaning that it has an entirely new architecture built using the 22nm production node.
Intel plans to split its product range into two distinct groups. The first group includes the company's desktop and notebook processors, while the latter is specially designed for Ultrabooks and drops the usual 2-chip platform approach that Intel has been using for quite some time in favor of a system-on-a-chip (SoC) design.
Desktop CPUs will feature either two of four processing cores with TDPs of 35, 45, 65 or 95 Watt, and will include a dual-channel DDR3/DDR3L memory controller, as well as GT2 or GT1 integrated graphics cores.
Mobile chips will be available in the same dual or quad-core configurations, but feature the more powerful Intel GT3 GPU, while the memory controller only supports DDR3L DIMMs.
As far as the Ultrabooks Haswell chips are concerned, these will be limited at supporting dual computing cores.
The TDP of Intel's upcoming system-on-a-chip devices will be set at 15W, while the rest of the notebook processors are rated as 37, 47 or 57 Watt parts..
Other features include support for the DirectX 11.1 API, support for the AVX2 instruction set, as well as a series of IPC improvements meant to increase single-thread performance. More details should become available in the coming months, after Intel starts the distribution of the first engineering sample CPUs.