Intel Describes Poulson Itanium Server Processor

The Itanium architecture was at the core of a certain dispute a couple of months ago, but whether or not the architecture would go on has been proven beyond doubt now that the Poulson is arriving.

Some may remember the rather heated debate, and subsequent court actions, that sprung from Oracle's decision to drop support for the Itanium server processor architecture.

Now, though, Intel has more or less removed any doubt as to whether or not the Itanium will go on by creating the Poulson chip.

The Santa Clara, California-based company has not actually released it, the same way no other chips, from it or rivals AMD, IBM, Oracle itself, etc. aren't getting launched at this year's Hotchips conference.

The first such unit was revealed earlier this year (2011), at the International Solid State Circuit Conference, and was an 8-core unit based on the 32nm manufacturing process and equipped with 3.1 billion transistors.

It boasts the QuickPath Scalable Memory Interconnects, as well as DDR3, compatibility with the 7500 Chipset and the Intel 7500 Scalable Memory Buffer.

The recent blog post went into somewhat more detail this once, and outlined three features, all of which are meant to push the 8-core, 12-wide issue architecture, to high peaks.

For one, new instructions are added to integer operations (expanded Data Access Hints, Expanded Software Prefetch and Thread Control).

Secondly, a better Hyper threading technology will support performance boosts with Dual Domain Multithreading, for a higher level of parallel computing performance.

Thirdly, the Instruction Reply Technology (on which the above multithreading feature relies) is a great enhancement to RAS and provides better error detection and instruction re-execution from instruction buffer queue, for fast recovery.

Users that want to take a direct look at the newly available data can drop by the IT giant's blog post, located here.