Intel Believes Chinese Processor Development Model Is Inefficient

Intel isn't worried about the advancements recorded by Chinese scientists in developing their own computer microprocessors, as the Santa Clara chip giant believes that the research approach currently employed for the design of these chips is inefficient.

This statement was made by Jesse Fang, the managing director of Intel Labs in Beijing, China, during an interview with the SemiAccurate publication.

The Intel representative is extremely impressed with the development of China's own CPU, but it believes that using only one group of people for both research and development is a bad idea as these tasks are very different.

According to Jesse Fang, research is about gathering and producing information, while developers have to turn all the data accumulated into a worthwhile product.

Intel's China Labs is one of the company's largest research institutes and employ about 100 scientists, which represent 10% of the company's total number of researchers.

The Labs mainly focus on embedded technologies, such as those used in tablets and smartphones.

For the last couple of years ICT, an institute under the Chinese Academy of Sciences, has been working on developing the Loongson CPU, which is based on an MIPS architecture with a set of 200 instructions designed to accelerate x86 emulation.

This architecture was included in a series of processors for general-purpose and embedded use, and this design was recently adapted in order to develop the Loongson 2H SoC, which targets mobile computing devices.

Outside of the CPU core, Loongson 2H also packs integrated graphics, a memory controller and all the functionality found traditionally inside the south bridge controller.

Just like the previous 2G revision of the chip, the Loongson 2H also uses a 4-way superscalar core with out-of-order execution based on the MIPS64 instruction set. Its power consumption is estimated at 4W when running at 1GHz and the chip also includes 64/64KB L1 cache and 512KB of level 2 cache.