Intel and TSMC Go for Advanced High-k Technology

The International Electron Devices Meeting surely was a good place for Intel to boast their newest technological breakthrough. The company have described their 45-nanometer logic technology, the first to integrate in high-volume manufacturing process high-k/metal gate transistors. They were not the only ones however to achieve spectacular results, as Taiwan Semiconductor Manufacturing Co. (TSMC) also reported successful results, but on a 32-nanometer architecture.

Intel's technology includes transistors featuring a high-k gate dielectric with a 1 nm electrical oxide thickness, along with dual-band edge metal gates and third-generation strained silicon. According to the manufacturer, they have managed to obtain the highest drive currents known for NMOS and PMOS devices.

Intel Corp. researchers speaking at this week's International Electron Devices Meeting (IEDM) described its 45-nm logic technology that for the first time incorporates high-k/metal gate transistors in a high-volume manufacturing process. The technology relies on trench contact-based local-routing, nine layers of copper interconnects with low-k ILD and 193-nm dry patterning lithography. After they have successfully eliminated cadmium and nickel from their production line, Intel has announced that the newly-developed technology also eliminates lead from the packaging process.

Intel has announced the first functional 45-nm 153-Mb SRAM almost two years ago, and the technology is currently in mass-production stage. TSMC has also reported a 32-nanometer low power foundry technology to use low-standby transistors, analog/RF functions and Cu/low-k interconnects. Their achievements are oriented towards mobile system-on-chip applications.

The company states that this is the smallest functional prototype of a SRAM testing probe to hold 2 Megabits, built around the 32-nanometer technology. In order to achieve an ultra-high density SRAM cell, the company engineers used 1.2 NA/193-nm immersion lithography in a double patterning technique.