14 DAY TRIAL // During yesterday's pre-briefing for the Spring Developer Forum, Intel's senior vice president Pat Gelsinger gave the first details regarding the chip manufacturer's upcoming technology at the 32-nanometer scale.
According to Gelsinger, the first 32-nanometer chip will be based on the Westmere micro-architecture, a 32-nanometer die shrink to Nehalem. It will be part of Intel's tick-tock processor development model, with a micro-architecture update in the first year, followed by a brand-new micro-architecture in the second.
The Westmere micro-architecture update will increase the transistor density over the Nehalem silicon, which would dramatically increase the new chip's performance and energy-efficiency, by shrinking and improving the existing micro-architecture.
The "Tock" will deliver a completely new silicon, built on the latest technology achievements in the silicon industry. As part of the 32-nanometer "tock", Intel plans to release the second 32-nanometer chip, codenamed "Sandy Bridge". It is expected to arrive on the market during 2010. Intel did not detail upon the 32-nanometer processors, but Gelsinger mentioned the fact that the Sandy Bridge chip will come with a major upgrade to the instruction set that comes with it.
As far as the technical details are correct, the Advanced Vector Extensions (AVX) seems to be some sort of SIMD (Single Instruction, Multiple Data) on steroids. The SIMD is a technique used to achieve data parallelism, similar to the vector processor implementations. If common SIMDs are 128 bits wide and can handle four single precision or two double precision floating point numbers, the AVX would double the figures, which would result in increased throughput and energy efficiency.
Gelsinger also made it clear that the Advanced Vector Extensions will not be available in the Westmere chips. The new technology will be implemented in the 32-nanometer Sandy Bridge chips only, that will offer support for 256-bit vector operations.