14 DAY TRIAL // The arrival of Core 2 Duo brought INTEL and its CPUs back into the light. However, the company has not based its upcoming processor design solely on the development of Core 2 Duo. The upcoming 45nm architecture is significantly different from the Penryn CPU (which is essentially a 45nm C2D) in terms of processing power but also memory controller, this segment being a weak point of the current Core 2 architecture.
Most of you who watch INTEL's roadmap releases probably know that Nehalem CPUs will use a new platform architecture which will do away with bus architecture. In an effort to improve the available bandwidth, INTEL's memory controller will feature point-to-point serial buses (currently called CSI - stands for Common Serial Bus). As weird as it may seem, this architecture is similar to the Hyper-Transport technology used by AMD or even PCI Express (in terms of p2p transfer).
As a matter of fact, INTEL wants to have full control over the internal structure of the CPU and in practice they will try to offer different levels of cache and bandwidth for different CPUs without having to include a hardware limitation in the chip itself. AMD CPUs can control the HT link speed or even disable the HT bus, but INTEL wants to go a step further. Because they have produced a theoretical design that can work with 3 DDR channels, each capable of controlling a DDR3 line.
A quad-core based on the Nehalem design will be able to deliver an impressive throughput (about 38.4GB/s when using PC3-1600 memory). At the moment, it is unknown whether the memory controller will be integrated into the CPU or it will remain a part of the chipset (Core 2 Duos do not integrate a memory controller).
Unfortunately, they will probably have to do just that. And while it will provide some serious advantages (high bandwidth, low latency) it will also mean that every new type of DDR will require a new type of CPU (the same happened with AMD and its 939 / AM2 CPUs). The first Nehalem-based cores are expected to come out at the beginning of 2009. Let's hope that they can find a solution to the onboard controller until then, as AMD is also working on an improved DDR controller able to use DDR3 too. And they are not very far from producing a decent solution that could give them the upper hand in the bandwidth wars.
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