INTEL Will Produce New Itanium 2 CPUs

For those of you who don't know a thing about Itanium or EPIC (Explicitly Parallel Instruction Computing) you can read various articles which detail the design of Itaniums and the impressive revenues brought by the server grade CPU each year (about $3.5 billion). The internal architecture of the Itaniums was developed especially to offer a decent alternative to IBM's Power PC series and as a result, the floating point performance of INTEL's CPU was and still is legendary.

Diane Bryant, vice president of Intel's enterprise group, released several details regarding the upcoming Itanium versions. Currently, the Montecito core runs on a 533MHz FSB but the upcoming Montvale will work at a higher 667MHz FSB. No details regarding the manufacturing process of Montvale were released, but Bryant said that it will also top out at a core speed of 1.66GHz with a total of 24MB of L3 cache.

Tukwila will probably be INTEL's first Itanium-based quad-core. With roughly twice the horsepower of a Montecito, the CPU won't need discrete memory controller as the company will introduce its CSI technology (Common System Interface). In essence, CSI is similar to AMD's HT in terms of usability so there will be no surprises in that area.

Tukwila will also come with even larger caches and a feature dubbed "Double device data correction" (DDDC). DDDC works just like a failsafe mechanism which can stop a certain chip from working if that particular chip produces errors. Derived from the ECC standard, DDDC will also be able to work with more than one faulty chip per Dram module.

Last but not least, Bryant talked about 32nm Itanium chips dubbed Poulson. This architecture could integrate more than 4 cores per die and it will also have enough space for an even larger cache. INTEL plans to skip the 45nm process for Itanium chips but 32nm CPUs might not come out until the fall of 2008.

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