14 DAY TRIAL // At this year's International Electron Device Meeting (IEDM), IBM researchers are due to detail the fabrication of a 2GHz graphene integrated circuit built using a CMOS-compatible manufacturing process technology.
Graphene is two-dimensional allotrope of carbon made from a hexagonal lattice of carbon atoms and their bonds.
As a result, the material is just one atom thick and scientists expect it to pave the way for the production of some of the smallest transistors possible.
Apart from its reduced footprint, graphene also brings a series of other advantages over silicon (the material used for fabrication integrated circuits) such as a greatly improved electron mobility, high current density as well as better saturation velocity, making particularly attractive for high performance circuits.
However, working with carbon-based materials is extremely difficult and can be highly problematic when introduced in a wafer fab.
These problems have limited the use of graphene to single devices and simple integrated circuits, but the paper IBM is going to present at IEDM will describe a new manufacturing technology based on CMOS-compatible fabrication using 200-mm diameter wafers for building such chips.
In order to surpass the issues posed by graphene, IBM's method relies on inverting the usual manufacturing process and define gate structures first on silicon wafers and then transfer graphene layers fabricated using chemical vapor deposition to the silicon.
After the graphene areas are defined, IBM is able to finalize the construction of FET structures by attaching drain and source contacts to the graphene.
The end result is a proof-of-concept RF frequency doubler circuit, which demonstrated a conversion gain of approximately 25dB at an output frequency of 2 GHz.
As mentioned earlier, IBM will present its research at the International Electron Device Meeting, which is scheduled to take place between December 5 and 7 in Washington DC. (via EETimes)