IBM and 3M Plan to Develop New Adhesives for 3D Semiconductors

IBM and 3M announced earlier today that the two companies are working on developing a new type of adhesive that can be used to package semiconductors into densely stacked silicon “towers,” making possible the construction of 3D chips composed from as much as 100 separate silicon layers.

According to IBM and 3M, such stacking would allow for dramatically higher levels of integration for computer and consumer electronics chips.

As a result of this advancement, processors could be tightly packed with memory and networking, to create a computer chip up to 1,000 times faster (at least in theory) than today’s fastest microprocessor enabling more powerful smartphones, tablets, computers and gaming devices.

The joint research started by the two companies tackles some of the most important issues faced by 3D stacking, one of the most important being the development of new types of adhesives.

These must be specially developed so that they can efficiently conduct heat through a densely packed stack of chips and away from heat-sensitive components such as logic circuits.

“Today's chips, including those containing ‘3D’ transistors, are in fact 2D chips that are still very flat structures,” said Bernard Meyerson, VP of Research, IBM.

“Our scientists are aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor – a silicon ‘skyscraper.’

“We believe we can advance the state-of-art in packaging, and create a new class of semiconductors that offer more speed and capabilities while they keep power usage low -- key requirements for many manufacturers, especially for makers of tablets and smartphones,” concluded the company's rep.

No timeframe has been posted regarding the development of these adhesives, but the companies stated that their goal is to bond entire wafers using this technology.