In a display of force, IBM today announced the newest member of the Power Architecture family of microprocessors, the new PowerPC 970MP. This new edition of the Power PC family is actually the dual core version of the PowerPC 970FX.

The IBM PowerPC 970MP microprocessor builds on the proven 64-bit IBM Power Architecture family and is designed for entry level servers as well as to provide new levels of performance and power management for the embedded marketplace.

Using 1MB of L2 cache for each of the two 64-bit PowerPC 970MP cores, the new processor has a double performance compared to the PowerPC 970FX. The frequency and voltage of both cores can be scaled downward to reduce the power during periods of reduced workload. For further power savings, each core can be independently placed in a power-saving state called doze, while the other core continues operation. Finally, one of the cores can be completely de-powered during periods of less stringent performance requirements.

IBM also announced today new low-power extensions to its award-winning PowerPC 970FX offering. This newest offering is targeted for clients who desire a low-cost 64-bit processor featuring high performance, a sub-20 Watt power envelope and SMP. The new offering is targeted to provide an operating power of 13W at 1.4 GHz and 16W at 1.6GHz under typical workloads. The microprocessor also provides power-saving features that system architects can use to dynamically control the system power.

Designed to run at frequencies up to 2.7 GHz, the PowerPC 970FX includes a 512KB L2 cache, provides native 64-bit and 32-bit application compatibility and uses a high bandwidth processor bus capable of delivering up to 7.1 GB/s to keep the processor core and the SIMD/Vector engine fed with data. The processor core can dispatch five instructions per cycle, and issue one instruction per cycle to each of its ten execution units, including two fixed point, two floating point, two load store, two vector and two system units. The L1 instruction cache holds 64 KB, the L1 data cache holds 32 KB, and each processor has its own dedicated 1MB L2 cache.