14 DAY TRIAL // Ex AMD-owned foundry, along with its partners, is going to demonstrate an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) manufacturing process, using the Gate First High-k Metal Gate (HKMG) approach.
Remember when we told you that GlobalFoundries is going to produce volume 28nm chips this summer? Well, it has already started.
The Super Low Power (SLP) manufacturing process is mainly targeted for low-power chip solutions, especially like those used in mobile phones and tablets.
Usually, the Super Low Power (SLP) manufacturing process is the first stage of the 28nm manufacturing development or better said, these chips are the first early results.
For an IC designer like Nvidia or Qualcomm this is very important, as both companies have low-power mobile chips that can benefit from SLP’s fastest time to market (TTM).
The SLP process is also the most affordable implementation, and in the current case it offers certified results for Low-Medium performance solutions clocked around 1500 MHz.
This would be a very good alternative manufacturing solution for Qualcomm’s insufficient volume problems that the company is experiencing at TSMC.
This is indeed a preferable option, and the company is actively analyzing the situation, like we reported here.
SLP offers twice the gate density while being a lower cost technology in terms of the performance elements utilized to boost carrier mobilities.
The foundry touts full scaling from current 45/40nm designs in terms of power and performance.
This means that when taking a 40nm design and moving it onto GlobalFoundries’ 28 nm manufacturing process, the chip designer will usually achieve the same performance / clock frequency, while having doubled the transistor density of the chip.
This usually translates into two things. The new chip is twice as small with lower power consumption, and maybe a higher frequency at almost double the number of chips per wafer.
Another situation is that when the chip can be more complex and there’s a compromise between the increased complexity and the power consumption and frequency achievable.
The foundry is claiming a 60% performance increase when compared with 40 nm chips, and up to 50% lower energy per switch and 50% lower static power.
Depending on the design, if the scaling is ideal, a 40 nm design will be able to work at 60% higher frequency while using the same amount of energy and dissipating the same amount of heat.
This is a very important aspect, as it tells the IC designer how much more performance it can get when sticking the new 28 nm chip inside current designs that are certified to provide a certain amount of current and can handle a certain amount of heat.