14 DAY TRIAL // Despite the imminent layoffs that will decimate 10 percent of Advanced Micro Devices' workforce, the company is still not giving up on the processor market. During yesterday's analyst meeting, AMD unveiled more than its revenue reports, and hinted at the company's upcoming 12-core processor micro-architectures to follow Shanghai.
The next silicon micro-architecture will be the Shanghai chip, that will be built on the 45-nanometer process node. The Shanghai chip will be extremely similar to the currently existing Barcelona B3 silicon stepping, except for the fact that it will come with a fully-fledged HyperTransport 3.0 clock generator.
Initially thought to be used for socket-to-socket communication, as well as for communication to the south bridge controllers, the HyperTransport 3.0 will only be used for inter-CPU communication. However, one of the engineers involved with the project claimed that the Shanghai technology would compensate for the HyperTransport 3.0 limitations, and even hinted at the fact that the inter-CPU communication will play a key role in the 45-nanometer technology refresh.
Next on AMD's roadmap is six-core micro-architecture, a Shanghai derivative that is currently known as Istanbul. The chip is AMD's response at the much-hyped six-core Dunnington chip to be released by Intel later this year.
However, six-core architectures are hardly news, given the fact that they exist and even function properly, as previously demonstrated by Intel during this spring's Intel Developer Forum. AMD needs to come with something better to impress the CPU market, and, according to reports from motherboard manufacturers, it will.
AMD will reportedly revive its older plans of introducing the twin-die per package technology in the upcoming Shanghai derivatives. The company thought of introducing twin-die packages since the release of its K8 micro-architecture. However, AMD ditched its plans and started promoting its "native quad-core" technology instead.
The twin-die Istanbul processor could raise the stake up to 12 cores per package, that would exchange data via the ultra-high-speed HyperTransport 3.0 bus. More than that, each chip will come with a dual-channel memory controller, that would allow a single core to emulate quad-channel memory functions.