As the annual MultiCore Expo opens this week, the first few steps taken towards improving the techniques for programming and measuring multicore processors begin to show their early fruits. More and more efforts are invested into multicore API, and the number of companies interested in the matter rises as well. Although the API was defined through the collaboration of several companies like Intel, Texas Instruments, Freescale or Impera, none of them announced the usage of the interface yet.
The MultiCore Expo (April 1-3) is focused on finding answers and solutions for the issues that the multicore implementations has brought with it. Some of the participants will present
their achievements in the multicore API, including Multicore Association, Polycore Software and Embedded Microprocessor Benchmark Consortium.
The Multicore Association started the research on defining a standard for embedded virtualization, after completing its work on a standard application programming interface for communications. Polycore Software developed a working version of the new multicore communications API and will try to demonstrate it in one of its tools. The Embedded Microprocessor Benchmark Consortium developed a new multicore processor benchmark and will show the results for running it on a variety of processors with 2 to 16 cores, yet the names of chips will not be revealed, but to the vendors.
The linking and synchronizing different kinds of cores in a processor is what API aims to provide. "The demo itself may not be very sexy, but it's fully functional and we're starting to get some traction," said Markus Levy, president of the Multicore Association. The setting of a standard for hypervisors that will control the way embedded processors virtualizes hardware resources is another goal for the Association. The group will first focus on issues as on-chip communications and debugging, in its way to defining what areas are fully developed for standards in the area. "There are more companies interested in the hypervisor issues than I expected," said Levy. "The processor guys are really into and the whole effort that was kicked off by Nokia Siemens Networks," he added.
One of the demos presented by EEMBC will show the results of running the same workload over two different dual-core processors and the way these results vary. Also, the way some workloads will not scale or scale linearly when run on the same multicore chip will be shown in other demos. "This is some of the most interesting benchmark data I have seen because very complex," said Levy who is also president of EEMBC. "You are dealing with systems-level issues such as OS scheduling techniques, context switching and varying peripheral sets," he said.
"The point right now is that to understand multicore performance you have to look at a lot of different things," Levy also said. According to him, "The HPC system developers, although long involved in multiprocessing designs, are challenged by new programming and debug complexities associated with practically unlimited scalability of cores. Embedded system developers are challenged by similar issues, but are also faced with very fundamental decisions such as determining when is the right time to convert their legacy applications to multicore."
As currently there is a set of benchmarks in use for the multicore chips, "Everybody is still struggling to determine what the right benchmarks are," said Jack Browne, vice president of marketing at MIPS Technologies. Dhrystone Mips on set-top boxes and Specmarks or Java user interface metrics are just some examples of them. Yet, the real-world applications-based benchmarks are more useful than synthetic ones, but system makers do not enjoy the idea of releasing their applications code for open testing.
In order to get feedback, EEMBC has released the benchmarks to one user. Through this, the terms of licensing its benchmarks will be decided in a meeting in mid-April. According to Levy, the new metrics seem to particularly interest system makers.
"Some of the telecoms OEMs are really struggling because they are finding in the shift from using two single-core chips to one multicore chip performance is going down. That's because they now have to share resources like caches," he said.