ARM Intros New LPDDR2 Memory Controller

Today, ARM announced the ARM PrimeCell low-power DDR2 (LPDDR2) dynamic memory controller, designed to provide a high-performance interface to LPDDR2 memory systems that can deliver twice the bandwidth of previous-generation LPDDR memory systems. The new controller, PL342, has been built to extend ARM's existing broad range of memory controllers and Physical IP, which will enable SoC designed to take full advantage of LPDDR2 memory.

 

“As LPDDR2 memory becomes more widely available, designers will be looking for new ways to bridge the performance gap between external memory and SoC processors, and take full advantage of advanced low-power memory systems. The ARM PL342 dynamic memory controller helps to maximize memory interface efficiency, minimize latency and ensure QoS, while minimizing energy consumption,” said Keith Clarke, VP Fabric IP, ARM. “ARM is committed to continued innovation in interconnect and peripheral IP to deliver integrated, optimized solutions for SoC backplanes.”

 

The company's new memory controller comes to support the emerging LPDDR2 memory, which is designed as a low-power memory technology for mobile and embedded designs, to offer higher speed, lower-voltage operation, larger capacities and lower pin count, compared with previous generation LPDDR memory.

 

The company has also revealed that its new memory controller, aside from providing a modular design that enables it to be adapted for use with many types of dynamic memory, will also be an early adopter of the DFI (DDR PHY Interface) 2.1 specification, because of the fact that ARM is a contributing member of the industry consortium that defines the DFI specification.

 

In addition to the new PL342 memory controller, ARM is also offering other new products to its memory controller family, all of which support DFI. These include a new version of the PL340 DDR/LPDDR memory controller with LPDDR-NVM support, and a new version of its PL341 DDR2 dynamic memory controller, which features ECC (Error Correcting Code) support.